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DRAM

DRAM interfacing

This documents what was necessary to interface with the 32 MB SDRAM on the BeagleWire. The important parameters for this chip:

  • tCK: The clock frequency, usually shared with the FPGA or interface (100 MHz)
  • CAS latency: 2 clocks at 100 MHz, 3 clocks at 166 MHz
  • tRCD: Active Command to Read/Write command. 2 or 3 clocks (same as CAS latency)
  • tRAS:
  • tCAS

Single byte write

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Note that the first byte of data is sent along with the column address.

Single byte read

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There is a minimum tRCD, but not a maximum. This means that the tRCD can be extended, so for SPI bus interfacing it should be possible to pre-select the row and bank as soon as those values are known, and then update the column when the later byte is received.

Also note that the incoming data is clocked on the rising edge, but the values should change while the clock is low. This might require a phase locked clock.

2018 Hardware

Last update: November 8, 2020